The present invention is in the field of material removal techniques, and relates to a system and method for surface planarization.
With the scaling of the dimensions of microelectronic devices, known as “Moors Law”, surface planarization processes used in the fabrication of such devices become more and more critical. A highly integrated semiconductor device is a stack of transistors, contacts and growing number of metal layers.
All back end of line (BEOL) metal layers are fabricated using “dual damascene” DD process, that includes chemical/mechanical polishing (CMP) at the final stage. This CMP process not only planarizes the surface of the entire wafer, but also creates the required thickness of metal lines (controlling resistivity of wires). Similar CMP approach is being applied to creation of the contacts, gates (replacement gate process) and is planned to be used for the creation of the replacement fins. All these surface planarization processes applied at various stages of fabrication are “stop-on” the layer type of CMP, where entire process can be described as at least two stages, where at the first stage (bulk removal) planarization is usually performed until the target layer is not reached, and at the second stage overpolishing is applied to the structure resulting from the first stage in order to ensure complete material removal and to achieve the desired thickness of the target layer.
During the CMP process, the exposed surface of a substrate is typically placed against a rotating polishing pad (disk pad or belt pad), which can be either a standard pad (having a durable roughened surface) or a fixed-abrasive pad (having abrasive particles held in a containment media). The substrate is controllably loaded to push it against the polishing pad. A polishing slurry, including at least one chemically reactive agent (and possibly abrasive particles if a standard pad is used), is supplied to the surface of the polishing pad. A CMP process is implemented in several successive steps, including single- or multi-step “bulk” material removal stage, followed by single- or multi-step overpolish and/or buffing material removal stage.
FIGS. 1A and 1B exemplify the commonly used CMP tool arrangement 10 for performing such multiple successive CMP steps. As shown in FIG. 1A, a rotatable multi-head carousel 12 supports four carrier heads 14A, 14B, 14C and 14D each configured for holding the sample (workpiece), and is rotated about its axis to move the carrier heads with the sample between polishing stations Platen 1, Platen 2, Platen 3 and a transfer station 16. The carrier head can receive and hold a sample S, and press it against the polishing pad, and can also move the respective sample toward and away from the platen surface. During polishing, the carrier heads press their respective samples against the corresponding polishing pad, the platens are rotated about their central axis, and the carrier heads are rotated about their respective central axes and translated laterally across the surface of the polishing pad. The CMP tools arrangement may include one or more in-situ or integral metrology systems that operate to determine a change in the thickness of a film/layer on the sample. The in-situ metrology system is positioned such that measurements can be made in real-time and while the film is being polished; each polishing station can include an independent in-situ measurement system. Integrated metrology tool may be located in between the adjacent polishing stations such that the carrier head brings the sample to a sample holder of the integrated metrology tool. As shown, the sample S starts/enters the CMP tolls arrangement for removal of the top layer (target layer), and this is successively done by the “bulk” removal step performed by Platen 1, and two successive overpolish and buffing steps performed by Platens 2 and 3.
Thus, as shown schematically in FIG. 1B, the conventional CMP tool arrangement 10 includes a set of polishing stations with platens 14 including one or more stations for “bulk” removal steps and a few stations 14 for overpolish and/or buffing removal/planarization. Also included in the CMP tool 10 are cleaning and drying modules 18 and a dry metrology system 20.
General Description
Recent CMP technology developments, such as multizone pressure control, pad thickness control, pad conditioning, special slurries and others have improved CMP performance to a certain level, but this level is barely sufficient for the strict requirements of the current manufacturing technology, and is problematic for any change in the technology. Gas clustered ion beam technology (GCIB) was proposed (U.S. Pat. No. 8,654,562) for the fine tuning and/or correcting and/or improving of the CMP tool performance. This technique, although being aimed at improving the Within Wafer (WIW) thickness uniformity of CMP process, reduction or elimination of such detrimental CMP effects as erosion and dishing, and reduction or elimination of the density effects, unavoidably requires very expensive process equipment to “correct” wafer topography after the entire CMP process.
Usually, the best CMP performance is reached when process is used to remove a part of the layer to simply planarize the wafer surface (“stop-in” layer). In this case, optimal process conditions for single layer removal can be achieved with optimal high planarization slurries. More complex situation arises for “stop-on” layers that represent clear majority of the CMP process steps in current manufacturing process. All “stop-on” CMP steps (including but not limiting to Oxide CMP with stop on SiN, and SiN CMP with stop on Oxide, or Oxide CMP with stop on Poly-Si, W CMP with stop on Oxide, etc.) require multi stage processing with bulk removal followed by overpolish and/or buffing. Both stages are problematic, but especially the second stage where combined and controlled removal of multiple materials may be required. This task is difficult to achieve for all structures with different density in the semiconductor device.
There is accordingly a need in the art for a novel approach for material removal technique, which allows for more precise surface planarization which allows complete removal of the layer in “stop-on”, eliminating the need for the complicated overpolish step of the current CMP, as well as the above-mentioned proposed techniques for post CMP corrections.
In order to simplify understanding of the present invention, the following should be noted. The step termed “rough” material removal refers to removal of the majority of the bulk material, but not all bulk material. For the “stop-on” layer, “rough” CMP removal will leave on the entire wafer a thin layer of removed material. Typically, the amount of material that is left is in the range of 10-100 A, and presents a result of the recipe optimization process. The “fine” material removal refers to removal of the last part of the remaining material (current CMP “stop-on” point) and also all steps of overpolish and/or buffing that create the final profile.
As indicated above, the conventional CMP process includes rough material removal stage followed by a sequence of fine material removal stages. The difference in the rough and fine CMP procedures is in the parameters of CMP process, pad and slurry materials. However, during each of the CMP stages, a polish process is applied to the entire surface of the sample with the same polishing parameters for the respective stage.
The inventors have found that after completion of the rough CMP material removal stage, instead of the current fine material removal CMP stages a novel material removal can be implied that greatly simplifies the process and improves the resulting within the wafer variations, local and global flatness.
The novel fine material removal process of the invention can be applied after the rough CMP stage and is based on the knowledge of the remaining thickness of the layer on the sample (wafer), i.e. sample map. This novel fine removal process utilizes selective etching of the remaining thickness which is locally controlled by application of the external energy etched rate at each point of the wafer (i.e. etch map), etch rate being calculated based on the known remaining thickness, so that the remaining layer is accurately removed from all different density sites on the entire wafer at the same time. By this, all fine material removal CMP steps, including overpolish and/or buffing, are eliminated.
The localized selective etching of the invention also solves such CMP problems as scratches, and can make post CMP cleaning process easier.
Novel material removal/surface planarization technique of the invention can be implemented in a stand alone material removal system, or can be integrated with the conventional CMP system used for the “rough” material removal, e.g. may follow the rough CMP stage. So, the present invention may be used for the fine tuning and/or correcting and/or improving of a CMP tool performance, at various possible configurations.
Generally, the novel material removal (or surface planarization) technique of the present invention can be used for removal of any target material from substrates other than semiconductor wafers, such as plastics, glass, etc., and can be used in various applications, for example for manufacturing electronic components, such as LCD screens, MEMS, Systems on Chip (SOC), advanced memory and logic devices, power switches, etc.
The present invention utilizes a localized selective material removal. In this connection, the following should be noted. The term “selective” refers to the selective etch of the target material(s) while other materials remain intact (etch rate of target material is much larger than etch rate of other materials). The term “localized” refers to the differences in the etch rate created by application of the external field such as temperature field, on one or more selected/identified sites (locations) on the sample's surface to control material removal rate. The term “localized” may also refer to the external energy (temperature) sample (wafer) map that allows creation of user defined etch rate map. The term “localized material removal” is essentially different from the “mask” based approach when lithography is used to create the pattern on the sample that is being selectively etched only on the exposed sites. The localized material removal of the present invention utilizes “etch rate controlled” localized material removal on all sites/locations on the sample, i.e. the etch material is applied to the entire sample's surface while on the selected sites/locations the material removal is faster than in other surface locations.
In other words, according to the invention, the material removal from selective sites of the sample's surface by etching utilizes the entire sample's surface interaction with the etching material, but, contrary to the conventional approach, utilizes a pattern/profile of the etching rate within the sample, i.e. the etching rate varies within the surface according to a predetermined pattern. As a result, different locations of the sample's surface undergo different levels of material removal. Knowledge of the thickness of the layers on the sample before the treatment allows for determining the pattern that is required to achieve the target of accurate material removal on the different sites at the entire sample surface. In some embodiments, such etching rate pattern (varying etching rate) is achieved by applying to the sample's surface a corresponding localized energy distribution affecting the etching process, e.g. a temperature pattern. Thus, in some embodiments, the present invention provides for selective removal of a target material on a sample (e.g. semiconductor wafer) with the variable etch rate at each location on the sample defined by the local sample temperature, which results from local heating. Generally, the desired temperature pattern on the sample's surface can be achieved by applying a spatially varying external radiation/field.
It should be understood that the material removal technique of the invention can be applied to a sample through selective wet etch process, but can be also applicable to any other selective removal processes with high external energy dependence, e.g. temperature dependence. Also, as indicated above, the present invention can be used for partial removal of a target material up to the desired target thickness, as well as for complete removal of the target material or materials.
Thus, according to one broad aspect of the invention, there is provided a surface planarization system comprising: an external energy source for generating a localized energy distribution within a processing region, and a control unit for operating said external energy source to create, by said localized energy distribution, a predetermined temperature pattern within said processing region such that different locations of said processing region are subjected to different temperatures, providing that when a sample interacting with an etching material composition is located in said processing region, the temperature pattern at different locations of the sample's surface creates different material removal rates by said etching material composition.
In some embodiments, the external energy source comprises one or more heaters. The heater(s) is/are may be of type generating electromagnetic radiation. In some embodiments, the energy source comprises a matrix of heaters arranged in a plane in a spaced-apart relationship, such that actuation of selective heaters with required working parameters creates the localized energy distribution in the processing region. Such working parameters may include one or more of the following: heating temperature, pulsed or CW operational mode, duration of heating, heating pulse shape, a time pattern of pulses (heating pulse duration and delay between heating pulses).
The control unit comprises an energy controller utility comprising a data processor configured for receiving and processing input data and generating operation data to the energy source. This operation data is indicative of the temperature pattern to be produced by the energy source in the processing region. In some embodiments, the input data comprises a sample map corresponding to thickness profile of a layer on the sample, and the data processor of the control unit is configured for processing the sample map data, determining a corresponding etch map, and generating the corresponding operation data to the energy source. In some other embodiments, the input data comprises etch map data corresponding to a sample map indicative of thickness profile of a layer on the sample to be processed by the system. The control unit may be configured for communication with an external system for receiving said input data. Such external system may be inspection/measurement/metrology system or external storage device which receives data from such inspection/measurement system. Such system is referred hereto at times as inspection system and times as metrology system. It should be understood that for the purposes of the present invention the ability of such system to determine a thickness profile for the sample′ layer is required. The metrology system may be configured for optical metrology e.g. using spectrometry, reflectometry, ellipsometry, and any suitable combination of these techniques.
In some embodiments, the surface planarization system also includes an in-situ inspection module which is in data communication with a control unit of the temperature field source. The in-situ inspection module is configured and operable for measuring at least one parameter, being a parameter of the sample and/or of the etch material composition, and generating process control data to be used (by the control unit) for controlling working parameters of the energy source to maintain the required temperature pattern and to define end point of the planarization process, when required result is being achieved.
According to another broad aspect of the invention, there is provided a surface planarization system comprising: an external energy source capable of generating a localized energy distribution within a processing region; a support unit for supporting a sample in an etching solution, in said processing region; and a control unit for receiving input data indicative of a sample map, determining a corresponding etch map, and generating operation data for operating said energy source to create the localized energy distribution creating a predetermined temperature pattern in said sample, thereby causing a temperature dependent etching pattern within the sample.
According to yet another broad aspect of the invention, there is provided a processing system for processing samples progressing on a production line, the system comprising:
a material removal system configured for applying at least one “rough” material removal process to a sample's surface;
the above-described surface planarization system configured for processing said sample after being processed by the “rough” material removal system,
an inspection system configured for inspecting the sample and generating process control data enabling generation of operation data to said surface planarization system.
The inspection system may comprises an integrated metrology tool configured for applying measurements (e.g. optical measurements) to the sample before its processing by the surface planarization system, and generating the output data corresponding to a sample map or an etch map. The processing system may include an in-situ metrology module associated with the surface planarization system and configured and operable for measuring one or more parameters, including at least one parameter of the sample and/or at least one parameter of the etch material composition, and generating process control data for controlling working parameters of the energy source to maintain the required temperature pattern.
The material removal system may be configured for material removal by CMP.
According to yet further aspect of the invention, there is provided a chemical mechanical polishing (CMP) tool arrangement comprising: at least one CMP station for applying a rough CMP processing to a sample; and the above-described surface planarization system located downstream of the CMP station(s) and being operable for applying fine surface planarization, by said selective etch, to the sample.
According to yet another aspect of the invention, there is provided a method of processing samples (e.g. semiconductor wafers) progressing on a production line, method comprising:
applying a rough CMP processing to the sample, in at least one CMP step;
applying optical metrology measurements to the sample after said rough CMP processing and generating process control data indicative of a thickness profile for a target layer on the sample;
applying fine surface planarization to the measured sample, said fine surface planarization comprising: interacting the sample with an etching material composition, and applying energy to the sample during said interaction with the etching material composition thereby creating a temperature pattern in the sample determined in accordance with said measured thickness profile, said temperature pattern creating a corresponding etch map at the surface of the sample, such that different locations of the sample's surface are subjected to different material removal rates by said etching material composition.
More specifically, the present invention is useful in semiconductor industry for surface planarization of wafers, which is typically done by CMP, and is therefore exemplified below with respect to this specific application. It should, however, be understood, and explained above, that the principles of the invention are not and should not be limited to this specific application.